The present invention relates generally to electronic design automation (EDA) tools, and, more particularly, to an EDA tool for executing topological and functional checks on an electronic circuit design.
Electronic circuits typically include millions of components. Such complex designs of electronic circuits are verified for a desired topology and functionality by an electronic design automation (EDA) tool. An EDA tool implements various topological and functional checks, such as interconnect performance checks, register transfer level (RTL) integration checks, clock domain crossing (CDC) checks, and the like, for verifying the electronic circuit design.
A known method for performing the aforementioned checks by the EDA tool includes simulating the electronic circuit design based on predefined design rules. However, the stated method fails to check whether the electronic circuit design has the required topology and properties, and whether undesired effects, such as overlapping paths of the components of the ECD, are absent in the electronic circuit design. Further, the method fails to perform functional checks on the electronic circuit design. Other known methods that perform topological checks verify the electronic circuit design graphically by way of the EDA tool. To verify the electronic circuit design graphically, various topologies of the electronic circuit design are verified one after the other. In an example, to verify a first topology that includes first and second nodes (i.e., two different components of the ECD) that are not connected to each other, several test graphs are generated such that each graph verifies a possibility of a direct or indirect connection between the two nodes. However, the generation of multiple such test graphs affects the speed of operation of the EDA tool. Further, such methods fail to perform graph based functional checks on the electronic circuit design.
Therefore, it would be advantageous to have a system and method that executes graph based topological and functional checks on the electronic circuit design and overcomes the aforementioned problems.